Increases in processor performance and the development of multi-core, multi-threaded processors have led to a rapidly increasing need for more memory bandwidth and capacity. To keep up with the increasing demands for data bandwidth and capacity, memory subsystems have had to increase both their frequency of operation and density. Many conventional systems provide power management with system-level temperature control via feedback cooling systems and/or system-level voltage/current control. Cooling systems are designed to reduce the overheating of the memory subsystem as a whole. Designing cooling systems to provide sufficient cooling capacity for these high density memory systems can be difficult as the cooling systems have to keep up with the increasing density of memory chips.
High power consumption in mobile devices also remains a challenging issue. The high bandwidth requirements of high end mobile devices, for example mobile phones and PDAs, exacerbate the problem. A memory channel consumes different amounts of power depending on its power mode or state, but the power mode also affects the memory bandwidth. A “power down” state uses the least power as it shuts off the memory channel, but during the power down state, the memory channel cannot be accessed. Entering and exiting the power down state can also have a significant performance overhead. In an “operation” state the memory channel consumes more power but is ready to respond to memory requests.
There can be more than one level or power mode in the operation state of a memory channel. In general, levels with greater throughput or bandwidth have greater power requirements. Many current memory systems use wire bond or off chip double data rate (DDR) memory. The number of interconnects between the DDR memory and processors is limited, and thus supporting multiple channels with separate input/output and Vdd would be difficult. Other systems use a technique of powering down the memory channel. To power down the channel, the channel can not be accessed, and there is a performance overhead in entering and exiting the power down state.
Thus, it would be desirable to reduce the power consumption of the memory devices without having a significant impact on the memory bandwidth or capacity.